Integrated circuit approach, with a serpentine conductor track for circuit configuration selection

ABSTRACT

An integrated circuit includes a serpentine conductor track extending through a plurality of conductor layers and having ends coupled to first and second circuit elements, the ends being in opposing outermost ones of the conductor layers. The serpentine conductor track can selectively be made to be (i) continuous and electrically couple the first and second circuit elements together or (ii) discontinuous so that the first and second conductor elements are not electrically coupled. In the latter case, the discontinuity can be formed in any one of the conductor layers and a bridging conductor track is further formed in that one conductor layer which is coupled to the serpentine conductor track and which bypasses either of the first and second circuit elements. This structure has the advantage that circuit changes can be made in any conductor layer. It has particular utility in the implementation of module ID circuits, where it is desirable to change the output of a module ID circuit to reflect a circuit revision in the integrated circuit. The change in the module ID circuit to alter its output can be made in the same conductor layer as that used to make the circuit revision, so that no additional mask changes are needed other than in the mask used for implementing the circuit change.

RELATED APPLICATION

[0001] This is a continuation of U.S. patent application Ser. No.09/460,936, filed on Dec. 14, 1999, and entitled “An Integrated CircuitWith a Serpentine Conductor Track for Circuit Selection.”

FIELD OF THE INVENTION

[0002] The invention relates generally to conductor routing amongcircuit elements in an integrated circuit. More particularly, theinvention relates to structure and a method which facilitate changingcircuit operation in any one of the conductor layers in an integratedcircuit.

BACKGROUND OF THE INVENTION

[0003] Integrated circuits (“ICs”) typically have a substrate, an activeregion on the substrate containing a large plurality of circuit elementssuch a transistors, resistors, capacitors etc., and a region adjacentthe active region which has a plurality of conductor layers andinsulating layers interspersed between the conductor layers. Theconductor layers each include a large number of conductor tracks whichare used to provide power to the circuit elements, as well as for signalrouting between the elements.

[0004] During design and testing of an integrated circuit, or even afteran IC had been in production, it is often necessary or desirable torevise the circuit operation to remove faults or to otherwise improvecircuit operation. At the most severe end of the spectrum of revisions,the changes may require modifications to the masks which define thecontent and arrangement of circuit elements on the substrate. Morefrequently, however, the designer has anticipated potential problems andhas included sufficient circuit elements on the integrated circuit tofix the problem. For example, the designers may include a selection ofbuffer circuit elements to remove timing problems in the signal routing.It is then a matter of modifying the conductor routing so as to decoupleand/or couple certain of the circuit elements so as to implement thefix.

[0005] Additionally, many chip designs incorporate an identification(“ID”) module which is readable by software. The purpose of the moduleID is to allow software to identify the hardware and, based on the ID,configure the chip and the corresponding software. As the industry movesto systems on a chip design, where proven circuit modules are “pluggedinto” the IC, it will be desirable for each module to have acorresponding ID module.

[0006] When making a circuit fix/enhancement to a particular module, itwill typically be desirable to change the output of the module IDcircuit, so that software will read a different ID code reflecting thechange.

[0007] Traditional implementations of ID modules is done by RegisterTransfer Level (“RTL”) implementation of a module ID register. In otherimplementations, the ID module is not a register at all, but simplyconstants which can be read by the software. In the case of a constant,the ID can not be changed by altering routing in one or more of theconductor layers, and a full new mask set may be required to implementthe change in the ID. This is expensive in terms of cost of the mask setas well as in the schedule slippage required by the time to create newmasks.

[0008] Other implementations allow the value of the module ID to berevised through changes in routing in the metal layers. However, inthese known techniques, the required changes in the routing aretypically in layers which are different than the layers used toimplement the circuit fix which necessitated the revision of the moduleID. Thus, additional mask charges are required.

SUMMARY OF THE INVENTION

[0009] Generally speaking, according to one aspect of the invention, anintegrated circuit includes a plurality of circuit elements and aplurality of conductor tracks connected to the circuit elements, theplurality of conductor tracks being arranged in a stack of a pluralityof conductor layers, the stack being bounded by first and secondopposing outermost conductor layers. A cell includes a serpentineconductor track having a first end in the first outermost conductorlayer and a second, opposing end in the second, opposing outermostconductor layer. The serpentine track extends successively from thefirst end to the second end through any conductor layers between theoutermost conductor layers. The serpentine track further includescouplings which couple track portions of the serpentine conductor track,the couplings being alternately laterally offset from each other alongthe extent of the serpentine track through the conductor layers. Thefirst end of the serpentine conductor track is coupled to a first of thecircuit elements and the second end is coupled to a second of thecircuit elements. Furthermore, the integrated circuit has one of (i) theserpentine conductor path forming continuous electrical path between thefirst circuit element and the second circuit element, and (ii) theserpentine conductor path having a discontinuity in one of the conductorlayers such that the first and second circuit elements are not coupledto each other and the integrated circuit further including a bridgingconductor track in the same conductor layer as said discontinuity, whichbridging track couples said serpentine conductor track to bypass one ofsaid first and second circuit elements.

[0010] The serpentine conductor track situated between two circuitelements allows great flexibility in how these two circuit elements aredecoupled from each other. In particular, since the track extendsthrough all conductor layers, the two elements can later be decoupledfrom each other by creating a discontinuity in any of the conductorlayers that the serpentine track passes through. Furthermore, one of thetwo circuit elements can be bypassed with a bridging conductor trackwhich is situated in the same conductor layer. This means that thefunctionality of the two elements car be altered with a change in onlyone conductor layer, and which may be achieved in any of the metallayers. Alternatively, the two circuit elements may be originallydecoupled, and in a later revision coupled to each other.

[0011] In another aspect of the inventor, an ID module in an IC iscomprised by the above described cell with first and second circuitelements and the serpentine track. The circuit elements may be logicgates, such as inverters. The ID module may include a plurality of thecells in parallel, each having an input which receives a common logicsignal. Where the cells are configured identically, the output of eachcell will be identical. However, the output of the group of cells can beselected by controlling the configuration of the cells, which can bedone in any conductor layer. Additionally, where a circuit revision isaccomplished in another part of the integrated circuit by changing therouting in a certain conductor layer, the Output of the cell(s) of theID module can be revised in the same conductor layer. Thus, the circuitchange and the ID module change can be implemented with changes to onlyone mask. This ultimately reduces the cost attributed to the IC, bysimplifying changes to the ID module and reducing mask costs.

[0012] The invention also relates to a method of manufacturing an ICwith the above-described structure.

[0013] These and other objects, features and advantages of the inventionwill become apparent from the following detailed description and thedrawings, both of which are illustrative and not limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 diagrammatically illustrates an integrated circuit with anumber of circuit modules and corresponding ID modules;

[0015]FIG. 2 illustrates cells of an exemplary identification moduleaccording to the invention;

[0016] FIGS. 3(A)-3(E) are diagrammatic, side cut-away viewsillustrating various embodiments of the conductor routing of a cell ofFIG. 2; and

[0017] FIGS. 4(A)-4(E) are diagrammatic top views corresponding to FIGS.3(A)-3(E).

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0018]FIG. 1 illustrates an IC 100 having a plurality of circuit modules101, 103, 105. Each of the circuit modules has a corresponding module IDcircuit 101A, 103A, 105A. A circuit 107 provides a logic signal to eachof the module ID circuits. The module ID circuits are coupled to anoutput pin of the IC so that the output of each module ID circuit can beread by an external device.

[0019]FIG. 2 is a circuit diagram of an exemplary ID circuit 101A havinga plurality of cells (200 ₁-200 _(n)). Each cell includes an input (205₁-205 _(n)), a first circuit element (201 ₁-200 _(n)), a second circuitelement (203 ₁-203 _(n)) and an output (207 ₁-207 _(n)). Each of thecircuit elements is a logic gate in the form of an inverter. The cellsare arranged in parallel to provide an identification code at theoutputs 207 in response to a common logic signal applied to all of thecells at the inputs 205. For example, if n=5 and a logic “0” is appliedto each of the inputs 205, the ID code output will be (0 0 0 0 0) sinceeach cell is shown configured simply as a buffer. To change the code,one or more of the cells are configured to bypass one of the inverters.FIG. 2 shows the cell 200 ₁ optionally being configured to bypass thefirst inverter 201 ₁, as represented by the dashed bridging conductor209 ₁. Alternatively, a bridging conductor could bypass the secondinverter, such as illustrated with dashed conductor 209 ₅ for the cell200 ₅. If the fires and fifth cells were so modified and the input keptthe same, the output would then be (1 0 0 0 1). Generally, more cellswould be included in each ID module, such as 32 to form a 32 bit ID.

[0020] While FIG. 1 shows each circuit module having a respective IDmodule for each circuit module, this is for a system on a chipimplementation. ICs for other applications could have only some of thecircuit modules with ID module's, or only one ID module for the IC.

[0021] As is well known in the art, generally, individual circuitelements are formed on top of a substrate of the integrated circuit.Connections to the individual transistors, resistors, capacitors toprovide a source of potential as well as for signal routing areaccomplished with conductor tracks arranges in a plurality of layers.The conductor tracks are typically or a metal, such as an alloy ofaluminum or copper. The conductor layers are separated by anelectrically insulating layer, such as silicon dioxide as one of manyexamples.

[0022] FIGS. 3(A)-3(E) illustrate various embodiments of a cell 200 ₁ atthe conductor layer level in a side cut away view while FIGS. 4(A)-4(E)are corresponding top diagrammatic views. The cell can be seen in FIG. 3as having 6 layers of conductors defined by a first outermost conductorlayer m1, a second outermost conductor layer m6, and four interveningconductor layers m2-m4. Intervening insulating layers are not shown forpurposes of clarity. Nodes A, B and D are formed by “stacked vias”formed respectively at node A by vias VA1-VA5, at node B by vias VB1-VB5and at node C by vias VC1-VC5. As used herein ‘stacked vias’ means aplurality of aligned vias interconnecting conductors in a plurality ofdifferent layers. Some processes/layout software do not allow this andin such processes the vias will not be aligned with each other. Thus, inthis embodiment a connection can be made at nodes A, B and D in anyconductor layer. The input I1 i of inverter 201 ₁ is coupled to node Aby track TA6 at conductor layer m6 while its output I1 o is coupled tonode B by track TB6 also in conductor layer m6. Similarly, the output I2o of the second inverter 203 is coupled to the node D by track TD6 atthe upper conductor layer m6.

[0023] The node C has a special configuration which permits the firstinverter or second inverter to be electrically bypassed duringmanufacturing to change its output, to thereby change the cell outputand the module ID. The node C is formed by a serpentine conductor trackSCT having one end C1 in the upper conductor layer m6 coupled to thenode B and a second end C2 coupled to the input I2 i of the secondinverter in the lower conductor layer m1. The track SCT extends from theend C1 in layer m6 through successive conductor tracks in layers m5, m4,m3 and m2 to the lower conductor layer m1 to the second end C2. Theconnections between the tracks in layers m6 and m5 is made by a via VC5,and connections between tracks in successive lower layers is made byvias VC4, VC3, VC2 and VC1. As shown in FIG. 3(A) the vias VC5, VC3 andVC1 are laterally offset from the vias VC2 and VC4, forming twolaterally spaced columns of vias. Thus, the node C as illustrated inFIG. 3 is formed by serpentine or zigzag path which extends from end C1across the track portion TC6 in layer m6, through via VC5 to trackportion TC5, back across track portion TC5 to via VC4, through via VC4and across track portion TC4 to and through via VC3, back across trackportion TC3 in conductor layer m3, through via VC2 across track portionTC2, and through via VC1 and across track portion TC1 in the layer M1 tothe end C2. The significance of the structure of node C as opposed tothe other nodes is that it provides track portions TC5, TC4, TC3, TC2between the successive laterally offset vias VC5, VC4, VC3, VC2 and VC1.These portions along with track portions TC6 and TC1 can be providedwith a gap during manufacture so as to decouple the output of the firstinverter from the input of the second inverter in any conductor layer.

[0024] In the configuration of FIG. 3A, the first and second invertersare coupled in series. The logic signal for generating the ID code mayhe input at node A at any of the conductor levels. By reason of thestacked vias VA1-VA5, the signal will be supplied to the input I1 i ofinverter 201 on track TA6 (see also FIG. 4(A)). The inverted logicsignal will be produced at the output of the inverter 201 ₁. Theinverted output is supplied by track TB6 to the end C1 of the serpentinetrack SCT. Since the track SCT forms a continuous electrical path asshown in FIG. 3a, the track SCT provides the inverted output of inverter201 ₁ to the input of the second inverter 203 ₁. The output of theinverter 203 is provided at node D. The output of the cell so configuredwill be the same as the input.

[0025] Suppose that a change needs to be made to the circuitry of module101, and this change is effected by changing the routing of certainconductors in the conductor layer m3. Changing the conductor trackrouting in the layer m3 requires that a new mask be made to create thedesired routing. To reflect the change in the circuit module 101, itwill also be desirable to change the module ID code. This isaccomplished by changing the cutout of one or more of the cells 200₁-200 _(n) which make up the ID module 101A. The IC according to theinvention allows the necessary cell modifications of the ID module to bemade in the same conductor layer (in this case layer 3) and with thesame mask as used for making the change in the circuit module. Thisavoids the necessity of making more than one new mask. This isaccomplished during manufacture of the IC by creating a discontinuity inone of the track portions or the serpentine conductor track SCT of thecell(s) which need to be modified. In the embodiment of FIG. 3B, thediscontinuity is created to decouple the output I1 o of the firstinverter from the input I2 i of the second inverter. Additionally, anend of the track portion in which the discontinuity is formed must alsobe coupled to the node A so that the input signal is provided to theinput of the second inverter.

[0026] In FIG. 3(B), the track portion TC3 is provided with adiscontinuity in the form of a gap G3. An end TC3 ₁ of track portion TC3is coupled to the node A by providing a bridging conductor track BT3which extends in the conductor layer 3 to the conductor track TA3 ofnode A from end TC3 ₁ (see FIG. 4(B)). The connections of tracks TA6,TB6 and TC6 remain physically the some (no change) but are shown indashed lines to indicate that these conductor tracks no longer form thesignal path. If the logic input signal is provided at the track TA6, thesignal path then extends from track TA6, through vias VA5, VA4 throughtrack TA3, bridging track BT3 to point TC3 ₁, via VC2, across trackportion TC2, through via VC1 and back across track TC1 whose end C2 iscoupled to the input of inverter 203. Thus, the cell 200 ₁ has beenchanged from the buffer configuration of FIGS. 3(A); 4(A) to an inverterconfiguration.

[0027] FIGS. 3(C) and 4(C) show how a similar change can be made in thelowest conductor level m1 by providing a cap G1 in the track portion TC1and by providing a bridging track BT1 in the same conductor level m1around the first inverter from node A at track TA1 to end C2. In thiscase, the connection from node A essentially bypasses the track SCT.

[0028] FIGS. 3(D); 4(D) show an alternative embodiment in which theserpentine track SCT is used to bypass the second cell element, in thiscase inverter 203 _(i). In FIG. 3(D) a gap G5 is placed in the conductortrack TC5, which disconnects the output of the inverter 201 ₁ from theinput of inverter 203 ₁. The inverter 203 ₁ is bypassed by providing abridging track BT5 in the same conductor level m5. Thus, the signal pathextends from the node A through the inverter 201 ₁ across tracks TB1,TC1 and through via VC5 to point TC4 ₁, which point is coupled to node Dvia track BT5.

[0029] FIGS. 4(E); 5(E) similarly show the second inverter beingbypassed, but with different signal routing from the output of the firstinverter. In this case, the end C2 of the track SCT is coupled to thetrack TB1 and the end C1 is coupled to the input of the second inverter203, which is the opposite of the previous embodiments. The end C1 ofthe serpentine conductor track is coupled to the output of the firstinverter at the first conductor level m1 through the vias VB5, VB4, VB3,VB2, VB1. The point TC2 ₁ is coupled to the node D via a bridging trackBT2 in the second conductor level.

[0030] The above embodiments illustrate the flexibility of theserpentine conductor track according to the invention. As long as oneend is coupled to one circuit element at the first outermost conductorlevel and the other end is coupled to the other circuit element at thesecond, opposing outermost conductor level, then the serpentine trackcan be used to break the electrical coupling between the two devices inthe outermost conductor levels and any intervening conductor levels. Abridging track can then be placed in the same conductor level to bypasseither of the first and second circuit elements of the cell.

[0031] The alternating arrangement of the vias of the serpentineconductor track provide lateral space between the vias in which the gapcan be formed in any conductor layer. However, the footprint of thetrack can be quite small, depending on the technology. For example, thespacing between the even and odd numbers of vias can be as small as0.26μ for a 0.18 micron process. Favorably, the vias are arranged in twocolumns, but where space is not critical, other configurations could beused.

[0032] The invention is not limited to just the number of layers shownin the embodiment, but is applicable to technologies with more or less,and even or odd, numbers of conductor layers. Additionally, favorablythe “outermost conductor layers” will bound all of the conductor layerson the IC to allow the circuit revision to occur in any one of all ofthe conductor layers. However, as the technology expands to include ICswith ever greater numbers of conductors, it is feasible that sufficientflexibility will be achieved for some purposes when the serpentine trackspans less than all of the conductor layers on an IC.

[0033] It should be understood from the foregoing that cells caninitially be configured with one of the circuit elements bypassed, andthen in a later revision to the IC, the bridging conductor track removedand the gap deleted, so as to electrically couple the first and secondinverters together.

[0034] In the examples shown in FIGS. 3(A)-3(C) where the bridgingconductor is connected to node A, it should be clear that nodes B and Ddo not require stacked vias, or even that the conductors in thedifferent layers of nodes B, D be electrically connected. It is onlynecessary that any layer in node A be available to the bridgingconductor from the same layer in node C (having the discontinuity).Similarly, in the embodiments of FIGS. 3(c), 3(D), only the node Drequires stacked vias. The stacked vias were shown in all embodiments atnodes A, B and D, however, since typically cell elements arestandardized in a cell library, and from a uniformity standpoint, it isadvantageous that both ends of the logic element be available in allconductor layers by stacked vias.

[0035] While inverters have been shown as the logic gates, other logicgates could be used as well.

[0036] The structure and method described above are not limited to theuse of module ID circuits, but in any situation where it would bedesirable to change the connection of two circuit elements in any one ofa plurality of conductor levels. For example, where changes in one partof a circuit are foreseen to require changes in a second part of acircuit, it would be desirable to include the serpentine structure inthe second cart of the circuit so that the changes therein can be madein the same conductor layer and with the same mask as the changes in thefirst part of the circuit.

[0037] It is understood in the art that routing software is used to layout the conductor tracks in the various conductor layers. Generally, thesoftware is designed to align the vias, as shown for example with nodesA, B and D. Thus a layout engineer would have to “hard block” thisfunctionality in the software to generate the serpentine track. Also,the original layout of the cell, in the first version of the IC, wouldhave to be provided with obstruction layers in all conductor layers toavoid the typical software routing tool room routing over the cell. Thisguarantees that a metal fix will always be available in any metal layer.

[0038] The technology by which the invention is made is not importantand any of the standard bipolar or CMOS processes can be used.

[0039] Although preferred embodiments of the present invention have beenshown and described, it will be appreciated by those skilled in the artthat changes may be made in these embodiments without departing from theprinciples and spirit of the invention, the scope of which is defined inthe claims.

[0040] The many features and advantages of the invention are apparentfrom the detailed specification and it is intended by the appendedclaims to cover all such features and advantages which fall within thetrue spirit and scope of the invention. Since numerous modifications andchanges will readily occur to those skilled in the art, it is notdesired to limit the invention to the exact construction and operationillustrated and described, and accordingly all suitable modificationsand equivalents may be resorted to, falling within the scope of theinvention.

What is claimed is:
 1. An integrated circuit, comprising: a stack ofconductor layers, the stack including a first conductor layer, an innerconductor layer, and a second conductor layer respectively carryingfirst, inner and second conductors; a plurality of circuit elementsrespectively connected to the first and second conductors; a serpentineconductor track including the first, inner and second conductors andhaving a discontinuity in the inner conductor; and a bridging conductortrack located in the inner layer and arranged to connect the serpentineconductor track to bypass one of the circuit elements.
 2. The integratedcircuit of claim 2 , further including an identification circuit adaptedto generate an identification code, the identification code beingdefined at least in part by at least one of the circuit elements and thebridging conductor track.
 3. The integrated circuit of claim 2 , whereineach of the circuit elements includes a logic gate.
 4. The integratedcircuit of claim 1 , further including an identification circuit adaptedto generate an identification code, the identification code beingdefined at least in part by at least one of the circuit elements and thebridging conductor track, and wherein the identification code is passedthrough said at least one of the circuit elements.
 5. The integratedcircuit of claim 1 , further including couplings adapted to intercouplethe first, inner and second conductors between the layers, the couplingsarranged alternately laterally offset from each along the serpentinetrack through the respective conductor layers.
 6. The integrated circuitof claim 5 , wherein the first, inner and second conductors are alignedover one another.
 7. The integrated circuit of claim 1 , wherein theinner layer is a buried layer on one side of each of the first andsecond conductors, and further including: an identification circuitadapted to generate an identification code, the identification codebeing defined at least in part by at least one of the circuit elementsand the bridging conductor track, and wherein the identification code ispassed through said at least one of the circuit elements; and couplingsadapted to intercouple the first, inner and second conductors betweenthe layers, the couplings arranged alternately laterally offset fromeach along the serpentine track through the respective conductor layers,and wherein the first, inner and second conductors are aligned over oneanother.
 8. An integrated circuit, comprising: a stack of a plurality ofconductor layers, the stack including a first conductor layer and asecond conductive layer; a first circuit having a first node and asecond node; a second circuit having a first node and a second node; afirst plurality of vias interconnecting conductors on a plurality ofdifferent conductor layers, the first plurality of interconnectingconductors coupled to the first node of the first circuit; a secondplurality of vias interconnecting conductors on the plurality ofdifferent conductor layers, the second plurality of interconnectingconductors coupled to the second node of the second circuit; and aserpentine conductor track having (i) a first end in the first conductorlayer, (ii) a second end in the second conductor layer, the serpentineconductor track forming a continuous electrical path extending seriallyfrom the first end to the second end through the different conductorlayers, and (iii) couplings between the different conductor layers, thecouplings being alternately lateral offset from each along the extent ofthe serpentine track through conductor layers.
 9. The integrated circuitof claim 8 , wherein the first and second circuits are circuit elements.10. The integrated circuit of claim 8 , wherein the first conductorlayer is an outermost conductive layer, the second conductor layer is anopposing outermost conductive layer, and the stack of a plurality ofconductor layers is bounded by the first conductor layer and the secondopposing outermost conductive layer.
 11. An integrated circuit,comprising: a first conductor layer; a second conductor layer; a firstcircuit element; a second circuit element; at least one serpentineconductor track; and one of the serpentine conductor track forming acontinuous electrical path between the first circuit element and thesecond circuit element, and the serpentine conductor track having adiscontinuity in at least one of the conductor layers such that thefirst and second circuit elements are not coupled to each other and theintegrated circuit further including a bridging conductor track in thesame conductor layer as said discontinuity, which bridging track couplessaid serpentine conductor track to bypass one of said first and secondcircuit elements.
 12. A method for manufacturing an integrated circuit,comprising: forming a stack of conductor layers including first, innerand second conductors with conductors respectively on each of the first,inner and second conductors, providing a region for forming a bridgingconductor track located in the inner layer and connecting the serpentineconductor track to bypass one of a plurality of circuit elements;forming a serpentine conductor track to interconnect a plurality ofcircuit elements in the integrated circuit, the serpentine conductortrack including the first, inner and second conductors respectivelyalong first, inner and second conductor layers of the stack of conductorlayers; wherein forming the serpentine conductor track includes formingthe inner conductor to include a lateral segment that can be severed toprovide a discontinuity in the serpentine conductor track and to therebyprovide an altered configuration of the integrated circuit; andproviding an integrated circuit configuration by selecting at least oneof: (i) severing the lateral segment and thereby providing thediscontinuity in the serpentine conductor track; and (ii) forming thebridging conductor track at the region of the inner layer and therebyconnecting the serpentine conductor track to bypass one of the circuitelements.
 13. The method claim 12 , wherein the serpentine conductortrack and the plurality of circuit elements form part of anidentification circuit, and wherein providing an integrated circuitconfiguration defines an identification code for the integrated circuit.14. The method claim 13 , wherein each of the circuit elements includesa logic gate.
 15. The method claim 13 , wherein the identification codeis passed through at least one of the circuit elements.
 16. The methodclaim 13 , further including forming couplings intercoupling the first,inner and second conductors between the layers, the couplings arrangedalternately laterally offset from each along the serpentine trackthrough the respective conductor layers.
 17. The method claim 13 ,wherein the first, inner and second conductors are aligned over oneanother.
 18. The method claim 13 , wherein providing an integratedcircuit configuration includes severing the lateral segment and therebyproviding the discontinuity in the serpentine conductor track.
 19. Themethod claim 13 , wherein providing an integrated circuit configurationincludes forming the bridging conductor track at the region of the innerlayer and thereby connecting the serpentine conductor track to bypassone of the circuit elements.
 20. The method claim 13 , wherein providingan integrated circuit configuration includes severing the lateralsegment and thereby providing the discontinuity in the serpentineconductor track, and forming the bridging conductor track at the regionof the inner layer and thereby connecting the serpentine conductor trackto bypass one of the circuit elements.
 21. A method for manufacturing anintegrated circuit, comprising: using a stack of conductor layers,forming a serpentine conductor track to interconnect a plurality ofcircuit elements, the serpentine conductor track including first, innerand second conductors respectively along first, inner and secondconductor layers of the stack of conductor layers; forming adiscontinuity in the inner conductor; and forming a bridging conductortrack located in the inner layer and arranged to connect the serpentineconductor track to bypass one of the circuit elements.